Telairity Launches H.264 HD Encoder
August 19, 2005
Telairity Semiconductor has announced its new video encoder for AVC (MPEG 4, Part 10/H.264).
Starting with the T1P2000 multicore processor, the first system-on-chip (SoC) to use the new architecture, Telairity 1's H.264 encoding solutions offer a small footprint and low cost for broadcast-quality H.264 video compression, according to the company. Telairity-1 architecture combines five independent vector/scalar cores, a video controller, and a DRAM controller supporting an I/O bandwidth up to 5.3 Gbps in a single multicore SoC. Each vector/scalar core features four vector pipes with independent hardware, an independent scalar unit, 128 KB of on-chip vector SRAM, a 4 KB vector SRAM data cache, an 8-KB scalar scratchpad memory and a 32-KB instruction cache. The Santa-Clara-based company will allow customers to modify or add new algorithms to customize the encoder.
The encoder has a clock rate of 668.25 or nine times the 74.25 MHz 20-bit video standard.