Why should we do AC-coupling on SDI and, how does AC-coupling degrade our SDI signal? In past experiences, many engineers asked me this simple question, and because we are familiar with AC-coupled signals, we usually forget about the theory behind our design choice and we apply the rule of thumb. I think that we behave this way a lot of the time. Maybe it is because we don't always have enough time to think about the theory!
Like me, you maybe discovered this signal degradation in the lab. I had worked for many years in a telecommunications business, and when I joined a well-known broadcast business in Montreal, one of my first assignments was to work on an optical-to-electrical converter. At that time, small form-factor pluggable (SFP) was a new concept in telecommunications. So why don't we use it for broadcast? I ordered a few parts to play with.
My first conclusion was that everything worked perfectly except with the pathological signal. (The AC-coupling wasn't the only problem; laser control loop and other problem were present in the SFP.) Then, I contacted the SFP manufacturer to correct the automatic power control loop; it sent me a new SFP with a slow control loop. I investigated the circuit in detail since the behaviour of the SFP was not improving. The AC-coupling capacitor value was 0.1µF because the module was used for 8b/10b encoding a well-balanced signal. I did find the remaining problems of the pathological signals in my SFP, but I faced a bigger problem: The manufacturer didn't want to change the layout with bigger capacitors.
I hope you will enjoy this quick explanation of the AC-coupling capacitors versus the beautiful pathological signal. As a designer, you can find articles on how the equalizer should handle the pathological signals, but the information about how blocking capacitors react versus pathological is not accessible on the Internet. This article explains the behavior of the blocking capacitor and shows why the pathological signal is affected.
Pathological signal generation
The pathological signal is a result of the coding scheme of the SMPTE standards. Two functions are used in SDI to encode the signal. The reason for these two polynomials is simple: to encode the signal without significantly increasing the bandwidth. In many cases, the 8b/10b is used to encode the signal and to balance the number of 1's and 0's (called DC-balance or zero DC-component). Those encoding schemes increase drastically the bandwidth, 25 percent for the 8b/10b. Today, the data communications and telecommunications companies are looking to 64b/66b to reduce this increase to a reasonable 3.125 percent.
The scrambling and non-return-to-zero-inverted (NRZI) are used to increase the transition density in the serial data stream, but some sequences create the undesired pathological signals. The NRZI also allows the receiver to decode an inverted stream; remember that the goal of the scrambler and the NRZI was the minimization of the overhead created by the encoding. Take as an example the 8b/10b encoding; from the 8 bits of data, the encoder creates 10 bits. With the 8b/10b encoding, the data stream has a 25 percent speed overhead due to the encoding, compared to 0 percent with the NRZI. However, the 8b/10b encoding creates a DC-balance data stream. The SDI encoding is accomplished after the concatenation of two functions:
As a consequence of this encoding scheme, runs of 0's and 1's can appear in the data stream. Applying 300hex followed by 198hex during the video active line produces 19 high (or low) data followed by a unique 1 low (or high) data. This run isn't a problem if this occurs once, compared to 66b/64b that can produce 66 consecutive identical data (CID). The problem with the SDI encoding is the repetitive sequence of 300hex followed by 198hex; it produces the pathological signal, a specific shade of magenta, which occurs in the active portion of the line. (See Figure 1.)
Blocking capacitor effect
A blocking capacitor with a termination resistor forms a high-pass filter. This filter should have a low cutoff frequency to minimize the distortion on the signal. (See Figure 2.)
When long runs of consecutive identical bits are presented to this high-pass filter, a voltage drop occurs, resulting in low-frequency jitter. This jitter is pattern-dependant. It is called pattern-dependant jitter (PDJ) or data-dependant jitter (DDJ). (See Figure 3.)
To minimize the PDJ, the 3dB cutoff frequency should be set correctly. This frequency is directly related to the capacitor (Cb) and the resistor (Rt). If you use new components with internal termination, you have lesser values of Rt. The goal is to use a smaller capacitor size with the desired capacitance to minimize reflections. The following equations solve the capacitor's value:
t is the discharge time: NCID * bit period.
τ is the RC constant (Cb and Rt ), twice Rt considering the driver impedance.
Vpp is the voltage swing.
tr is the rise time of the signal (20 percent to 80 percent).
Note for designers: If you ever simulate AC-coupled high-speed traces, you will always see an option like “skip x symbols at the beginning.” Remember that the AC-coupling capacitor is discharged at the beginning of the simulation, so you will have the same behavior; your signal will not be DC-balanced, even with 8b/10b. The simulator will skip the first eye diagram to ensure that your simulation is relevant.
If the pattern was only limited to one occurence, the blocking capacitor for SDI encoding should be really small. In the SMPTE-259 (270Mb/s) and SMPTE-292 specifications, the pattern can be repetitive up to 720 or 1920 times respectively. The difference between the number of 0's and 1's over a long time can be called the cumulative bit difference (CBD); over a line the CBD is large.
Eye diagram after the blocking capacitor
With the previous explanation, we can clearly understand why the pathological problem is not the CID but the DC unbalance over the line period (CBD). In other words, the capacitor charge will not stay at the midpoint for the entire line. This effect moves the unique 1 or 0 over the time far from the decision point, creating errors. Figures 4 and 5 show the eye diagram at the end of the line for the 270Mb/s pathological signal (half line).
Another way to represent the blocking capacitor effect is in frequency domain. Compare the frequency spectrum of the pathological signal versus a random stream applied to the blocking capacitor circuit. (See Figure 6.) Note the power close to DC for the pathological signal (red). All the energy below the cutoff frequency will be attenuated, reducing the SNR and thus degrading the bit error rate (338Hz for the 4.7µF and 265 kHz for the 6nF).
Possible changes on Cb and Rt
The previous waveform demonstrates the pathological frequency spectrum versus a perfect random signal with 1 and 0 balance. To preserve the maximum SNR, the cutoff frequency of 338Hz appears to be a good choice. Changing the internal termination from 50Ω to 75Ω and keeping the same cutoff frequency, now the value of Cb is 3.3µF. (See Figure 7.) This 3.3µF capacitor can be smaller in size and can be more stable in temperature.
DC-coupled versus AC-coupled
So why don't we do DC-coupled circuits instead of AC-coupled? The DC-coupled could be a great solution, but you should be aware of a few key characteristic of your drivers and receivers. First is the common mode voltage of your driver; every high-speed driver is swinging around a DC voltage on each wire. As example, the output of your equalizer could swing from 3.3V to 2.9V. (See the datasheet of the part you use for more precise information.) If you use a new FPGA to deserialize the signal, you might have a voltage common mode of 1.2V with an allowed swing of +/-400mV. You can clearly see that your equalizer outputs will not work with your FPGA inputs. In this specific case, AC-coupling is one of the easiest solutions.
Here are the key points to consider before deciding to go DC-coupled:
- Known driver: no DC offset possible, ie on the same board or in the same system;
- Common mode voltage (Vcm) of the driver is included in the receiver input common mode voltage;
- All combinations of Vcm positive and negative swings of the signal are included in the receiver tolerance.
This article shows the blocking capacitor's effect on the pathological signal. This effect can be controlled by designing the system to have a low 3dB cutoff frequency and by ensuring an equal number of 1's and 0's over time. With SDI encoding, the second option isn't possible; the designer should set the cutoff frequency very low to keep the SNR as high as possible or use DC-coupling when the technology and design permit it.
Renaud Lavoie is president and CEO of Embrionix.
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