Bit-serial digital video distribution - TvTechnology

Bit-serial digital video distribution

Michael Robin's look at bit-serial video distribution focuses on techniques to move digital signals between devices and systems
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Figure 1. 4:2:2 bit-serial digital distribution model. Click here to see an enlarged diagram.

The 4:2:2 bit-parallel digital signal is distributed using a shielded twisted 12-pair (balanced) cable of conventional design. The bits of the digital words that describe the video are transmitted in a parallel arrangement using 10 (eight for eight bits/sample) conductor pairs. An 11th (ninth for eight bits/sample) pair carries a parallel clock.

Figure 2. Formation of the eye pattern from superimposed binary patterns. Click here to see an enlarged diagram.

The 4:2:2 digital signal bit-parallel equipment interconnection is adequate for short distances and simple, point-to-point signal distribution patterns. It is inadequate for large teleproduction centers with complex signal distribution patterns where the high cost of multicore cables and the large size of multipin connectors come into play and bit-serial digital distribution is preferred.

The SDTV bit-serial distribution standard

The SDTV SMPTE standard 259M specifies the characteristics of the bit-serial interface for 525/60 and 625/50 digital equipment operating with either component digital signals or 4fSC composite digital signals. It has applications in a television studio using 75Ω coaxial cable lengths not exceeding the amount specified by the equipment manufacturer. Typically, a 4:2:2 bit-serial digital signal loss of 30dB at the clock frequency at the receiver input is acceptable.

Figure 1 shows a block diagram of a 4:2:2 component digital bit-serial distribution. The source encoder is the conventional set of three (E'Y, E'B-Y, E'R-Y) A/D converters followed by a time division data multiplexer. The output of the multiplexer is a sequence of CB, Y, CR parallel 10-bit words. The channel encoder transforms the bit-parallel digital signal into a bit-serial digital signal suitable to transmission via the chosen medium (for example, 75Ω coaxial cable).

Figure 3. Block diagram of an SDTV 4:2:2 component digital serializer . Click here to see an enlarged diagram.

The signal is corrupted by thermal noise, which in a studio environment is contributed by the receiver input stage. The receiver channel decoder deserializes the received bit-serial signal and recovers the bit-parallel digital video signal. Poor signal-to-thermal-noise ratio at the receiver input may affect its capability to reconstruct the original signal, resulting in bits in errors or missing altogether.

The output of the receiver channel decoder is the original sequence of CB, Y, CR. The signal decoder is the conventional demultiplexer followed by a set of three D/A converters recovering the original analog component video signals (E'Y, E'B-Y, E'R-Y).

The serializer converts the bit-parallel digital signal into an analog physical representation. The eye pattern (or eye diagram) is used in specifying and verifying the characteristics of a bit-serial digital signal. The name results from the appearance on a storage oscilloscope of sections of digital symbol patterns superimposed on one another.

Figure 4. Oscilloscope display of an eye diagram. Click here to see an enlarged diagram.

Figure 2 shows the formation of an eye pattern from superimposed binary patterns. For an infinite-bandwidth system, the transitions from zero to one to zero are instantaneous and, consequently, the eye is rectangular. A practical system has a finite bandpass, resulting in transitions with a slower risetime and the familiar eye shape. Bit-serial signals are specified in terms of eye amplitude, risetime and decay-time, overshoot, and jitter.

The serializer (channel encoder)

Figure 3 shows the simplified block diagram of an SDTV 4:2:2 component digital serializer. It performs several functions implemented in dedicated ICs. These are:

Figure 5. Block diagram of a 4:2:2 component digital deserializer. Click here to see an enlarged diagram.

  • Parallel-to-serial conversion. This is performed by a 10-bit shift register that is clocked at 10 times the input rate.
  • Scrambling. The scrambling randomizes long sequences of 0s and 1s as well as repetitive data patterns that could result in clock regeneration difficulties in the deserializer. It helps eliminate the DC content and provides sufficient signal transitions for reliable clock recovery in the deserializer.
  • Conversion from non-return-to-zero(NRZ) to non-return-to-zero-inverted (NRZI). The scrambler can produce long runs of ones. These are converted to transitions by an NRZ-to-NRZI converter.

  • Table 1. Interface specifications. Click here to see an enlarged diagram.

  • Serial clock generation. The serial clock is generated using a voltage-controlled oscillator (VCO) operating at the bit-serial clock frequency (270MHz). Its frequency is derived from the parallel clock frequency (27MHz) and is controlled by a phase-locked loop (PLL) circuit. The derived VCO frequency control voltage is low-pass-filtered by an unspecified filter that determines the capture range and the hold range of the VCO and removes high frequencies from the control voltage. This allows the serial clock to follow low-frequency jitter or drift (wander) of the parallel clock as well as correct for a temperature-related drift of its own.
  • Cable driving. Following the NRZI converter, there are 75Ω source impedance unbalanced active line drivers for each output, unlike baseband video, where multiple outputs can be split from a single active driver.

Figure 4 shows a typical eye diagram as displayed on a wideband oscilloscope. Table 1 on page 40 lists some interface specifications.

Figure 5 shows a simplified block diagram of a 4:2:2 component digital deserializer. The system performs several functions implemented in dedicated ICs. These are:

  • Cable-loss equalization. An automatic cable-loss equalizer for high-frequency (>8MHz) and low-frequency (<8MHz) losses introduced by the coaxial cable. The equalization capability is a manufacturer's choice.

  • Table 2. Deserializer specifications. Click here to see an enlarged diagram.

  • NRZI-to-NRZ conversion. This process is the reverse of the process taking place in the serializer.
  • Descrambling. This process is the reverse of the process taking place in the serializer resulting in the recovered data being identical to the original data.
  • Clock recovery. The bit-serial digital signal is self-clocking. This means that it carries no specific clock. Rather, the clock is recovered by counting the zero-to-one-to-zero transitions in the signal. The clock recovery relies on the fact that the scrambled NRZI datastream contains a large number of transitions.

Current state-of-the-art technology relies on PLL concepts for locking the receiver data extraction circuitry to the incoming data. PLLs have a specific bandwidth determined by the low-pass filter at the output of the phase detector. The bandwidth should, ideally, be narrow to achieve a high level of noise immunity. Narrow-bandwidth PLLs have a correspondingly narrow pull-in (capture) range, requiring a highly stable crystal-controlled VCO to stop it from drifting beyond the PLL capture range. Noise immunity and capture range are conflicting requirements in the design of PLL circuitry. The current dominant technology relies on a PLL bandwidth of the order of 2MHz. This means that the VCO will follow incoming signal jitter frequency-domain components up to a limit of 2MHz. It also means that the VCO free-run frequency may drift up to a limit of 2MHz from the wanted frequency and the PLL will correct for this frequency drift. The regenerated serial clock feeds the NRZI-to-NRZ converter and the descrambler. It also feeds a timing generator that regenerates the 27MHz clock required by the serial-to-parallel converter.

The deserializer (receiver channel decoder)

  • Serial-to-parallel conversion. The serial-to-parallel converter recovers the original parallel data for further processing.
  • Regeneration of a reclocked bit-serial signal. This function, available with some designs, permits the regeneration of a high-quality noise-free bit-serial signal from the corrupted input signal. The low-frequency jitter of the input signal, inside the PLL bandwidth, will be carried through, but the high-frequency jitter will be eliminated.

Table 2 lists some deserializer specifications. The bit-parallel digital signal interface has been superseded by the bit-serial digital signal interface, which is far more practical in large installations. The SDTV model, as described above, has served as a model for HDTV implementations with some application-related approaches.

Michael Robin, a fellow of the SMPTE and former engineer with the Canadian Broadcasting Corp.'s engineering headquarters, is an independent broadcast consultant located in Montreal, Canada. He is co-author of Digital Television Fundamentals, published by McGraw-Hill and translated into Chinese and Japanese.

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