CMOS image sensors: Making HDTV cameras affordable
Today’s broadcasters are confronting challenges that arguably are the most daunting they have ever faced. On the one hand, tight budgets and shrinking resources are forcing deepening cutbacks.
Above: JVC and Ikegami are the first camera makers to take advantage of Rockwell Scientific’s CMOS image sensor in their new HD cameras. Pictured above is JVC’s prototype CMOS HD camera.
Yet, there has never been as much competition in our shrinking world, nor as strong a need to do more with less. To top it off, there is the pending mandate to shift from good old NTSC to HDTV. In essence, the choice is to have lunch or to be lunch. Fortunately, the semiconductor industry – the engineer’s equivalent of the US 7th Cavalry – has been winning similar battles for several decades.
The tireless march of Moore’s law has transformed consumer electronics, and will transform broadcast and ENG cameras in much the same way. Broadcast professionals have already benefited from complementary metal-oxide-semiconductor (CMOS) application-specific integrated circuits (ASICs). Now, CMOS image sensors permit creative and affordable HDTV production. Ultimately, they will yield programmable electronic film with unprecedented video sensitivity.
Keep the noise down
CMOS-based image sensors, like the ubiquitous charge-coupled devices (CCDs), are made with silicon and use photodiodes to detect light. But the similarities end there. They differ radically in the way they handle the resulting electric charges.
CCDs noiselessly shift the photo-generated charge from one charge-handling bucket to the next until the packet reaches the output structure. Unfortunately, this structure generates noise in the electronic bandwidth of the ensuing video signal. The supporting video ICs remove some of the noise – specifically, the reset noise from the “sense” capacitance that converts the charge into a voltage – using correlated double sampling. The supporting ICs then digitize the video stream. The noise not removed by these ICs remains in the video stream. This noise rises with frequency at about 3dB per octave and restricts the camera’s signal-to-noise ratio (S/N).
This photo shows the ProCamHD 3530 CMOS image sensor in a standard 65-pin PGA package. Three such sensors are incorporated into the new HD cameras being developed by JVC and Ikegami.
By contrast, CMOS sensors can handle the signal in a way that significantly reduces noise. In the lowest-noise CMOS sensors, the photo-generated current is immediately converted to a voltage at a relatively narrow electronic bandwidth. Successive stages of analog and digital processing in the CMOS imaging system on chip (iSoC) suppress the temporal and spatial noise to the level allowed by the underlying CMOS technology.
The photolithography process that semiconductor manufacturers used in the early ‘90s to “print” the pixels and supporting circuits in nascent CMOS image sensors was crude by today’s standards. The size of the smallest structures on these sensors was about one micron. And each CMOS chip held no more than about one million transistors.
Nevertheless, these devices still look modern compared to the transistor-based metal-oxide-semiconductor (MOS) sensors that originally competed with CCDs in the ‘70s and ‘80s in the “luggable” camcorders of the time. During that era, MOS-sensor pioneers struggled to produce low-quality video using only tens of thousands of transistors.
In stark contrast to those MOS-based ancestors that used transistors of only one polarity or the other, the latest MOS-based sensors use CMOS technology and deep-submicron photolithography for structures no larger than 0.25 micron. The same technology that produces ever-faster, ever-cheaper, multi-GHz microprocessors also produces CMOS iSoCs image sensors with ever-increasing performance and sophistication. CMOS technology offers both n-type and p-type transistors and, consequently, provides ultra-low-power operation of the self-contained subsystems. And each CMOS iSoC can contain over 100 million transistors.
More support, free logic
At the 2003 NAB show, Rockwell Scientific (Camarillo, CA) announced the commercial availability of its CMOS iSoC image sensor, the ProCamHD 3530. Ikegami and JVC are now incorporating this chip into professional HD cameras.
Figure 1. This simplified block diagram of CMOS iSoC image sensor shows the functional blocks that perform signal detection, analog-to-digital conversion and signal processing.
Figure 1 shows a block diagram of the chip, which converts the photons collected at each pixel into 12 digital bits. About one dozen functional blocks perform signal detection, analog-to-digital conversion and signal processing. By contrast, the support circuitry in a CCD sensor includes only the unity-gain analog amplifier(s) necessary to pipe the analog video through one or more video taps. To facilitate higher composite video rates, the trend in CCD design is to simply include more video taps that must be electronically stitched together and equalized by the camera.
In sensor design, adding features is attractive only to the point at which their accessibility and the resulting camera operation become overly complicated. In this respect, CMOS technology has a further advantage over CCDs because the digital logic that simplifies multimode operation essentially comes free – except, of course, for the non-recurring design cost. Thus, Moore’s Law continually affects CMOS image-sensor development through ongoing performance improvements, relentless cost reductions, rapid growth of embedded functionality, and expansion of operating modes with easier operation.
Mixed signals, higher resolution
Some CCD camera designers and marketing teams are currently pushing interlace-mode imaging to reach f10 sensitivity at 2000 lux. To do this, they use two-line mixing (co-adding two adjacent lines) to double the signal strength. (Keep in mind that progressive-mode line mixing is not possible with CCDs.) But interlacing creates irreparable defects in the video. The outcome is much like buying a beautiful home that overlooks the local landfill. CMOS technology, on the other hand, allows analog, digital and analog-with-digital (i.e., mixed-signal) processing. This promises to deliver sensors with programmable multi-line mixing for both interlaced and progressive imaging later this year.
Perhaps even more importantly, CMOS cameras promise high-quality images even under adverse illumination. While the effective nine-bit resolution of CCD-based HDTV cameras is impressive considering the pixel size and video frequency, broadcast engineers nevertheless lament their sensitivity loss (one to two f-stops) compared to NTSC cameras. But CMOS provides a clear path for progressing beyond the current S/N benchmark of 54dB (f8 at 2000 lux) for interlaced HDTV cameras. CMOS’ smaller noise bandwidths and diverse signal processing options enable progressive-scan imaging with increasingly higher S/Ns – corresponding to 10- to 14-bit resolution – as the technology matures.
Figure 2. This graph shows the read noise and the corresponding theoretical S/Ns for two sensors that don’t use line mixing.
The plot thickens
Figure 2 plots the read noise and the corresponding theoretical S/Ns for two sensors that don’t use line mixing. (Line mixing can improve S/N by 3dB to 6dB beyond those shown in the graph.) One plot assumes that the detector’s quantum efficiency (QE) – its ability to intercept incoming photons of light and convert them to electrical charges – is 65 percent. For comparison, the other plot is for an ideal chip with a theoretical QE of 100 percent. The graph also shows the 3530 sensor’s S/Ns at 0-, 6- and 18dB gain. The total iSoC noise for this studio-grade sensor limits its S/N to 52dB at 0dB gain. Increasing sensor gain to 6dB boosts the S/N to 57.5dB. Pixel-limited sensor noise of three electrons at a gain of 18dB yields an S/N of 69dB and an ISO speed greater than 1600.
Considering the incremental HD CCD advances over the last decade, it is now clear that to similarly improve CCD-based cameras would require adding many output taps to each CCD at the expense of more camera complexity, higher power dissipation, shorter battery life and higher cost. In the meantime, the CMOS iSoC will further mature by advancing existing microlens technology (tiny lenses that sit atop each pixel), lowering the system-on-chip noise to the pixel-limited noise of three electrons, and applying line mixing (if not objectionable due to the associated degradation in vertical definition). This will clear the path to the first-ever, end-to-end 12-bit HDTV. In terms of electronic film speed, the ISO speed with CMOS-based HD cameras will improve from today’s 200 ISO to 1600 and beyond.
Les Kozlowski is chief technology officer and Markus Loose is manager of CMOS sensor design for the CIS Business Group at Rockwell Scientific.
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